ECE 511
Computer Architecture
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Readings:
Date
Topic
08/29
Dark Silicon and the End of Multicore Scaling
09/07
trace cache a low latency approach to high bandwidth instruction fetching
optimization of instruction fetch mechanism for high issue rates
09/12
Reducing Power Dissipation of Register Alias Tables in High Performance Processors
09/19
Assisted Execution
A Stateless Content-Directed Data Prefetching Mechanism
Execution-Based Prediction Using Speculative Slices
Going the Distance for TLB Prefetching
Lockup-Free Instruction Fetch Prefetch Cache Organization
Prefetching Using Markov Predictors
Simultaneous Subordinate Microthreading
09/21
dram-aware-caches
10/30
Performance of Processor-Memory Interconnections for Multiprocessors
11/02
SIMD.pptx
11/11
accelerators specialization emergin architectures.pptx
near memory processing