ECE 581: Advanced Analog IC Design
Handouts
Papers
D. B. Ribner and M. A. Copeland, “Design techniques for cascoded CMOS op amps with improved PSRR and common-mode input range,” IEEE Journal of Solid-State Circuits, vol. 19, no. 6, pp. 919-925, Dec. 1984.
T. Cho and P. Gray, “A 10 b, 20 Msamples, 35 mW pipeline AD converter,” IEEE Journal of Solid-State Circuits, Vol. 30, no. 3, pp. 166-172, March 1995.
S. Lewis et al, “A 10-b 20-Msample/s analog-to-digital converter,” IEEE Journal of Solid-State Circuits, Vol. 27, no. 3, pp. 351-358, March 1992.
F. Silveira and D. Flandre,“Operational amplifier power optimization for a given total (slewing plus linear) settling time,” Proc. Symp. on Integrated Circuits and Systems Design, 2002. pp.247-253, 2002.
K. Bult and G. Geelen, “A fast-settling CMOS op amp for SC circuits with 90-dB DC gain,” IEEE Journal of Solid-State Circuits, Vol. 25, no. 6, pp. 1379-1384. December 1990. Describes design of a gain boosted cascode amplifier.
M. Tian et al, “Striving for small-signal stability,” IEEE Circuits and Devices. Vol. 17, no. 1, pp. 31-41. January 2001.
Describes algorithm used for stability analysis (stb) in spectre.
Pollissard-Quatremere et al, “A modified gm/ID design methodology for deeply scaled CMOS technologies,” Analog Integrated Circuits and Signal Processing. Vol. 78, no. 3, pp. 771-784. March 2014.
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