Course Project: Pipelined Analog to Digital Converter Design

Project Description and Report Guidelines: (download pdf)

Ideal Pipelined ADC Model and Testbenches: (download)

Many ideal blocks in the library are modeled using Verilog-A, an analog behavioral description language. The language reference document for Spectre simulator can be found at following location on EWS machines.

/software/Cadence/MMSIM111/doc/veriaref/veriaref.pdf

Sample MATLAB Simulation Files

%Please use Matlab version equal or later than R2013a.

• Main MATLAB script for simulation : pipeline_1p5bit_sim.m

• Simulink model for simulation : pipeline_1p5bit_sim.slx

• MATLAB function for spectrum plot : plot_spectrum.m

• MATLAB function for DNL calculation : find_dnl.m