ECE 581: Advanced Analog IC DesignCourse Project: Pipelined Analog to Digital Converter Design
Project Description and Report Guidelines: (download pdf)
Ideal Pipelined ADC Model and Testbenches: (download)Many ideal blocks in the library are modeled using Verilog-A, an analog behavioral description language. The language reference document for Spectre simulator can be found at following location on EWS machines. /software/Cadence/MMSIM111/doc/veriaref/veriaref.pdf
Sample MATLAB Simulation Files%Please use Matlab version equal or later than R2013a.
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